1. Field of the Invention
The present invention concerns a nonvolatile semiconductor memory and, more particularly, an electrically erasable and programmable read-only memory (EEPROM).
2. Description of the Related Art
As a nonvolatile semiconductor memory device becomes more highly integrated in order to increase storage capacity and raise the operating speed, new problems appear. A nonvolatile semiconductor memory is constructed with a plurality of storage cells (memory cells), which are each composed of a floating gate transistor. Each floating gate transistor, in turn, consists of a floating gate, a control gate, a source and a drain. The storage cells are arranged in a matrix consisting of rows and columns. The control gates for each row of storage cells are all connected to a single shared word line while the drains for each column of storage cells are connected to a common bit line. A memory cell array will thus consist of a plurality of the storage cells together with a plurality of word and bit lines by which data is stored and read from the cells of the array.
In order to enhance the operating speed of a nonvolatile semiconductor memory, the data stored in the storage cells connected with a selected word line are simultaneously read out through the plurality of corresponding bit lines in what is called a page read. The data read out during the page read are stored into a plurality of data latches called page buffers. In contrast, the write operation (programming) is achieved by sequentially storing data into the page buffers through a data input/output (I/O) pad or terminal, and then simultaneously transferring the data stored in the page buffers into the storage cells connected to a selected word line. This method for writing data into a memory array is called page programming. The page read and programming operation are described in further detail in commonly-assigned Korean Laid-Open Patent Publication No. 94-18870 published on Aug. 19, 1994.
To describe the page read, programming and erasing operations in greater detail, page programming data into memory cells is achieved by applying a high level programming voltage, e.g. 18 V, to a word line connected to the control gates of the memory cells and a ground level voltage to the respective bit lines connected with the channels of the memory cells so that the voltage difference between the control gates of the memory cells and the channels causes electrons to penetrate the thin oxide film, otherwise known as the Fowler Nordheim Tunneling phenomenon, in order to reach the floating gate thereby changing the threshold voltage of the transistor controlled by the control gate. The erasing operation is achieved by reversing the process and applying an erasing voltage, typically 20 V, to a large block of memory cells and the ground level voltage to the word line connected to the control gates so that the voltage difference between the transistor wells of the cells and the control gates of the transistors causes the electrons stored in the floating gates to tunnel away from the floating gates in order to discharge the floating gates and once again change the threshold voltage of the transistors in the block. Since the threshold voltage of each memory cell has a negative or positive value depending on whether it is in a programmed or an erased state, the read operation is achieved by applying zero voltage to the control gate of the memory cell and sensing the voltage difference between the drain and source of the cell. This type of nonvolatile semiconductor memory is called flash memory and is described in the papers entitled "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme" and "A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM", IEEE Journal of Solid-State Circuits, Vol.30, No. 11, Nov., 1995.
FIG. 1 illustrates a conventional memory cell array with a control circuit, where the array has 8,192 rows and 4,096 columns for 32 megabits (4,096.times.8,192) of memory cells. The memory cell array is divided into blocks B1-B512 of 64K each (4096.times.512), where block B1 is shown in greater detail. The control gates of the storage cells are connected through 8,192 word lines and the drains are connected through 4,096 bit lines. The block B1 includes NAND cell units NU0, NU1, . . . , NU4095 wherein each of the NAND cell units consists of 16 storage cells MO-M15 connected in series between the source of a first selection transistor ST1 and the drain of a second selection transistor ST2. The drain of each first selection transistor ST1 is connected to a corresponding bit line BL0, BL1, . . . , BL4095 through a resistor (not shown). The source of the second selection transistor ST2 is connected with a common source line CSL.
In each of the row blocks B1-B512, the control gates of the first selection transistors ST1 for each of the NAND units NU0-NU4095 are all commonly coupled to a first selection line SSL. Similarly, the control gates of storage cells M0-M15 of each NAND units NU0-NU4095 are all commonly coupled to a corresponding word line WL0-WL15, respectively. And the control gates of second selection transistors ST2 are all coupled in common to a second selective line GSL.
The first selective line SSL is driven by a first row decoder 102A and the second selective line GSL is driven by a second row decoder 102B. Further, the even numbered word lines WL0, WL2, . . . , WL14 are also driven by the first row decoder 102A while the odd numbered word lines WL1, WL3, . . . , WL15 are driven by the second row decoder 102B. Even numbered bit lines BL0, BL2, . . . , BL4094 are coupled to lower page buffer 101B while odd numbered bit lines BL1, BL3, . . . , BL4095 are coupled to upper page buffer 101A. The upper page buffer 10A and lower page buffer 101B each have internal data latches which temporarily store input data signals received through the input/output pins of the semiconductor memory device in order to perform various functions, such as controlling the execution of data programming operations as well as read-out and erase operations.
FIG. 2 illustrates the physical structure of a row of stacked memory cells. In the physical structure, a second conductive n-type well 202 is formed on a first conductive p-type semiconductor substrate 201. A first conductive-type pocket well 203 is placed on the second conductive n-type well 202. Each of the memory cells has a floating gate 206 and a control gate 208 in an active region. The individual stacked memory cells are separated from each other by a field insulator film 204. The reference number 208 also represents a word line because all the control gates in a given row are connected to the same word line. The floating gate 206 and control gate 208 are separated from each other by insulator film 207, such as ONO (Oxide/Nitride/Oxide). An insulator film 209 is formed on the word line 208 and the bit lines BL0-BL4095 are formed on top of insulator film 209. The thin oxide film 205 represents the area where electrons tunnel through to the floating gate 206.
In the nonvolatile semiconductor memory of FIG. 2, the second conductive n-type well 202 and the first conductive-type pocket well 203 are electrically connected to each other and a ground potential voltage is applied to them in order to perform data programming operation. The high level programming voltage is applied to the word line 208 connected to the control gates of the memory cells and the data are input through the bitlines BL0-BL4095 which are connected to the channels of the memory cells.
When some of the memory cells connected to a selected word line are not to be programmed, the VCC or higher voltage is directly or indirectly applied to channels corresponding to the memory cells so as to prevent those cells from being programmed.
Note that as the capacity of nonvolatile semiconductor memories is continuously improved by integrating the memories on a very large scale, that there is necessarily a resulting increase in the number of memory cells connected to a single word line and, accordingly, an increase in the number of memory cells that required to not be programmed during a given programming operation. This increase in the number of cells that are not to be programmed leads, in turn, to an increase in the power consumption of the bitlines which supply the channel voltage that prevents the state of the memory cell from being programmed. In addition, when the channel voltage is dropped, the memory cells that are required not to be programmed can be erroneously programmed by the voltage change causing corruption of the stored data.
For a data erasing operation, the ground voltage is applied to the word line 208 connected to the control gates of the memory cells to be erased. The erasing voltage (20 V) is applied to the second conductive n-type well 202 which is electrically connected to the first conductive-type pocket well 203 thereby erasing the data in all the memory cells connected to the word line. The increased level of integration of the memory device results in a larger number of memory cells connected each word line which causes both greater power consumption and a deterioration of the reliability of the device because a larger number of memory cells must be erased or programmed in order to make a correct in a small amount of data.
U.S. Pat. No. 4,878,199 is directed to solving the problems described above for nonvolatile semiconductor memory. The nonvolatile semiconductor memory proposed in U.S. Pat. No. 4,878,199 has opposing first and second conductive-type wells that are formed on a substrate. The first and second wells each simultaneously form the same number of memory cells which are jointly connected to the corresponding bit and word lines. One of the first and second wells forms an auxiliary memory cell array, where a back bias voltage is applied to the auxiliary memory cell array in order to increase the threshold voltage of the memory cells and prevent the redundant data read-out and operating data of the auxiliary memory cell array that is necessary when changing data of the main memory array. Thus memory faults are avoided and the memory device is more reliable.
However, the above method suffers from the disadvantage that two memory cells must be provided for storing one bit of data which cuts the memory density achieved through large scale integration in half. Also, the breakdown voltage at the bit line junction of the auxiliary array must be raised above the value of the bit line voltage plus the back bias voltage in order to prevent breakdown of the memory cell transistors in the auxiliary array.
Generally, in the memory cell array area, a high level erase voltage of 20 V is applied to a large number of memory cells during an erase operation, and is thus transferred to the peripheral circuits outside of the memory cell array, which results in junction breakdown or destruction of the gate oxide films in the peripheral circuits. The entire area of the cell array is formed by n-type wells, and the pocket wells are p-type wells formed inside of the n-type wells so as to prevent the high voltage applied to the p-type wells from being transferred to the peripheral circuitry during the data erasing operation.
However, as the density of nonvolatile semiconductor memory devices is increased to improve capacity, the number of rows and columns of the cell array also increases, thus increasing the length of the word lines. Typically, the word lines of a nonvolatile memory are made of polysilicon which has a sheet which is on the order of several tens of ohms. When the length of the word line is increased, the resistance of the word line also becomes greater so that the programing or read-out voltage drops when it is applied to the farthest memory cells which malfunction as a result. In addition, the erasing operation is performed on the level of blocks B1-B512, which means that an entire block must be erased and reprogrammed in order to correct a single byte of data.
The number of memory cells within the each of NAND units NU0-NU4095 is usually eight or sixteen. In large scale integration, the memory density is increased by using 32 or 64 memory cells in a single NAND unit. The size of a page of memory is usually 512 bytes, whereby the block size is 4K bytes or 8K bytes. Currently, in order to correct one byte of data, the entire memory block of 4K bytes or 8K bytes must be erased and then reprogrammed. This process for data correction is not only complicated and time-consuming, but also shortens the operational life of the memory cells.
Furthermore, the increase in memory density also increases the number of memory cells connected to the same word line which causes the page size to increase. The number of memory cells connected to the unit string also increases resulting in an increase in block size. For example, in the case of a 256 Megabit NAND-type flash memory, the size of a page is 2K bytes, and if the number of memory cells of the unit NAND memory are 32, then the size of a block is 64K bytes.
Also, since the number of cells that must be erased and reprogrammed in order to correct a byte of data is increased, the power consumption to perform an erase is also increased and the cells which are not required to be erased and reprogrammed are considerably deteriorated in terms of the their operational lifetime due to the repeated erasing and reprogramming operations. Furthermore, in the worst case for erasing and reprogramming a block, when only one bit data needs to be reprogrammed and the remaining data are not required to be reprogrammed, the back bias voltage used to prevent cells from being reprogrammed must be applied to all the remaining bit lines, which also leads to power consumption and additional operation time for charging the additional bitlines.